CORE0=arm, CORE1=arm
Architecture select (Arm/RISC-V). The default and allowable values of this register are constrained by the critical boot flags.
This register is reset by the earliest reset in the switched core power domain (before a processor cold reset).
Cores sample their architecture select signal on a warm reset. The source of the warm reset could be the system power-up state machine, the watchdog timer, Arm SYSRESETREQ or from RISC-V hartresetreq.
Note that when an Arm core is deselected, its cold reset domain is also held in reset, since in particular the SYSRESETREQ bit becomes inaccessible once the core is deselected. Note also the RISC-V cores do not have a cold reset domain, since their corresponding controls are located in the Debug Module.
| CORE0 | Select architecture for core 0. 0 (arm): Switch core 0 to Arm (Cortex-M33) 1 (riscv): Switch core 0 to RISC-V (Hazard3) |
| CORE1 | Select architecture for core 1. 0 (arm): Switch core 1 to Arm (Cortex-M33) 1 (riscv): Switch core 1 to RISC-V (Hazard3) |